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Logic Synthesis and Verification Algorithms (1996 edition)

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Logic Synthesis and Verification Algorithms - Hachtel, Gary D, and Somenzi, Fabio
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Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more ...

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Logic Synthesis and Verification Algorithms 2013, Springer, New York, NY

ISBN-13: 9781475770360

Trade paperback

Logic Synthesis and Verification Algorithms 2006, Springer, New York, NY

ISBN-13: 9780387310046

1996 edition

Trade paperback

Logic Synthesis and Verification Algorithms 1996, Springer, New York, NY

ISBN-13: 9780792397465

1996 edition

Hardcover