Written by a stellar team of field experts, this title is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that allow VSLI designers, DFT practitioners, and students to master quickly System-on-Chip Test architectures, memory, and analog/mixed-signal designs.
Read More
Written by a stellar team of field experts, this title is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that allow VSLI designers, DFT practitioners, and students to master quickly System-on-Chip Test architectures, memory, and analog/mixed-signal designs.
Read Less
Add this copy of System-on-Chip Test Architectures: Nanometer Design for to cart. $98.64, good condition, Sold by Bonita rated 4.0 out of 5 stars, ships from Newport Coast, CA, UNITED STATES, published 2007 by Morgan Kaufmann.
Add this copy of System-On-Chip Test Architectures: Nanometer Design for to cart. $99.99, new condition, Sold by Booksplease rated 4.0 out of 5 stars, ships from Southport, MERSEYSIDE, UNITED KINGDOM, published 2007 by Morgan Kaufmann Publishers.
Add this copy of System-on-Chip Test Architectures: Nanometer Design for to cart. $180.59, new condition, Sold by Bonita rated 4.0 out of 5 stars, ships from Newport Coast, CA, UNITED STATES, published 2007 by Morgan Kaufmann.
