VLSI-Soc: From Systems to Chips: Ifip Tc 10/Wg 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-Soc 2003), December 1-3, 2003, Darmstadt, Germany
VLSI-Soc: From Systems to Chips: Ifip Tc 10/Wg 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-Soc 2003), December 1-3, 2003, Darmstadt, Germany
Effect of Power Optimizations on Soft Error Rate.- Dynamic Models for Substrate Coupling in Mixed-Mode Systems.- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.- Automated Conversion of SystemC Fixed-Point Data Types.- Exploration of Sequential Depth by Evolutionary Algorithms.- Validation of Asynchronous Circuit Specifications Using IF/CADP.- On-Chip Property Verification Using Assertion Processors.- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.- ...
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Effect of Power Optimizations on Soft Error Rate.- Dynamic Models for Substrate Coupling in Mixed-Mode Systems.- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.- Automated Conversion of SystemC Fixed-Point Data Types.- Exploration of Sequential Depth by Evolutionary Algorithms.- Validation of Asynchronous Circuit Specifications Using IF/CADP.- On-Chip Property Verification Using Assertion Processors.- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.- A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications.- Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans.- Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.- Optimizing SOC Test Resources Using Dual Sequences.- A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits.- Low Power Java Processor for Embedded Applications.- Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.- Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.- Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.- Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths.- Stuck-At-Fault Testability of SPP Three-Level Logic Forms.
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New. Trade paperback (US). Glued binding. 314 p. Contains: Illustrations, black & white. IFIP Advances in Information and Communication Technology, 200. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
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