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Modeling of Electrical Overstress in Integrated Circuits

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Modeling of Electrical Overstress in Integrated Circuits - Diaz, Carlos H, and Sung-Mo (Steve) Kang, and Duvvury, Charvaka
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Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools ...

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Modeling of Electrical Overstress in Integrated Circuits 2012, Springer, New York, NY

ISBN-13: 9781461362050

1995 edition

Trade paperback

Modeling of Electrical Overstress in Integrated Circuits 1994, Springer, New York, NY

ISBN-13: 9780792395058

1995 edition

Hardcover