Interconnect has become the dominating factor in determining system performance in nanometer technologies. This book is dedicated to this important subject. The primary purpose of this monograph is to provide insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. In this monograph, the effects of wire size, spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), ...
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Interconnect has become the dominating factor in determining system performance in nanometer technologies. This book is dedicated to this important subject. The primary purpose of this monograph is to provide insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. In this monograph, the effects of wire size, spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, shields, direction of the signals, and wire width for both the aggressors and the victim wires on system performance and reliability is thoroughly investigated. Also, parameters like driver strength has been considered as several recent studies considered the simultaneous device and interconnect sizing. Crosstalk noise, as well as the impact of coupling on aggressor delay is analyzed. The pulse width of the crosstalk noise, which is of similar importance for circuit performance as the peak amplitude, is also analyzed. We have considered more parameters that can affect the signal integrity and presented practical intensive simulation results. This book brings together a wealth of information previously scattered throughout the literature, presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. The practical aspects of the algorithms and models are explained with sufficient detail. It deeply investigates the most two effective parameters in layout optimization, spacing and shield insertion, that can affect both capacitive and inductive noise. Noise models needed for layouts with multi-layer multi-crosscoupling segmentsare investigated. Different post-layout optimization techniques are explained with complexity analysis and benchmarks tests are provided.
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