Dedication. Preface. Acknowledgment. List of Abbreviations. List of Figures. List of Tables. 1. Introduction. 1. High-Frequency Integrated Analog Filtering. 2. Multirate Switched-Capacitor Circuit Techniques. 3. Sampled-Data Interpolation Techniques. 4. Research Goals and Design Challenges. 2. Improved Multirate Polyphase-Based Interpolation Structures. 1. Introduction. 2. Conventional and Improved Analog Interpolation. 3. Polyphase Structures for Optimum-class Improved Analog Interpolation. 4. Multirate ADB Polyphase ...
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Dedication. Preface. Acknowledgment. List of Abbreviations. List of Figures. List of Tables. 1. Introduction. 1. High-Frequency Integrated Analog Filtering. 2. Multirate Switched-Capacitor Circuit Techniques. 3. Sampled-Data Interpolation Techniques. 4. Research Goals and Design Challenges. 2. Improved Multirate Polyphase-Based Interpolation Structures. 1. Introduction. 2. Conventional and Improved Analog Interpolation. 3. Polyphase Structures for Optimum-class Improved Analog Interpolation. 4. Multirate ADB Polyphase Structures. 5. Low-Sensitivity Multirate IIR Structures. 6. Summary. 3. Practical Multirate SC Circuit Design Considerations. 1.Introduction. 2. Power Consumption Analysis. 3. Capacitor-Ratio Sensitivity Analysis. 4. Finite Gain & Bandwidth Effects. 5. Input-Referred Offset Effects. 6. Phase Timing-Mismatch Effects. 7. Noise Analysis. 8. Summary. 4. Gain- and Offset-Compensation for Multirate SC Circuits. 1. Introduction. 2. Autozeroing and Correlated-Double Sampling Techniques. 3. AZ and CDS SC Delay Blocks with Mismatch-Free Property. 4. AZ and CDS SC Accumulators. 5. Design Examples. 6. Speed and Power Considerations. 7. Summary. 5. Design of a 108 MHz Multistage SC Video Interpolating Filter. 1. Introduction. 2. Optimum Architecture Design. 3. Circuit Design. 4. Circuit Layout. 5. Simulation Results. 6. Summary. 6. Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter. 1. Introduction. 2. Prototype System-Level Design. 3. Prototype Circuit-Level Design. 4. Layout Considerations. 5. Simulation Results. 6. Summary. 7. Experimental Results. 1. Introduction. 2. PCB Design. 3. Measurement Setup and Results. 4. Summary. 8. Conclusions. Appendix 1.Timing-Mismatch Errors with Nonuniformly Holding Effects. 1. Spectrum Expressions for IU-ON(SH) and IN-CON(SH). 2. Closed Form SINAD Expression for IU-ON(SH) and IN-CON(SH). 3. Closed Form SFDR Expression for IN-CON(SH) systems. 4. Spectrum Correlation of IN-OU(IS) and IU-ON(SH). Appendix 2. Noise Analysis For SC ADB Delay Line and Polyphase Subfilters. 1. Output Noise of ADB Delay Line. 2. Output Noise of Polyphase Subfilters. Appendix 3. Gain, Phase and Offset Errors for GOC MF SC Delay Circuit i and j. 1. GOC MF SC Delay Circuit i. 2. GOC MF SC Delay Circuit j.
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Fine. Trade paperback (US). Glued binding. 228 p. The Springer International Engineering and Computer Science, 867. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
Add this copy of Design of Very High-Frequency Multirate Switched to cart. $103.31, new condition, Sold by GreatBookPrices rated 4.0 out of 5 stars, ships from Columbia, MD, UNITED STATES, published 2010 by Springer.
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New. Trade paperback (US). Glued binding. 228 p. The Springer International Engineering and Computer Science, 867. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.