Chip Design for Submicron VLSI: CMOS Layout and Simulation

Good for learning about basic Chip Layout

As the author mentioned that the book is a basic introduction to submicron CMOS designs,you will find the book contents organized into short chapters with a level of details that one can study and understand within a short period.The software that comes with the book is a nice tool to start learning CMOS VLSI layout and simulation.It would be best to practice as you read and understand each section or topic.You can learn much from hands on by doing your own version of layouts or circuits for simulation.Each figure of a layout shown in the book is usually large enough to clearly see the details.Thus, you can try to recreate your own layout as seen from the figure.
Contents: 406 pages of content, Each chapter contains a short list of References and a few excercise problems at the end of each chapter.
- Chapter 1 Installing the Software (15 pages)
This chapter helps you to start with the learning tools or the software .Plan of the Book tells you briefly about what you can find in each chapter and suggests what you can learn.
- Chapter 2 Views of a Chip--Layers and Patterns (21 pages) The chapter introduces the world of a chip designer at physical silicon level. 2.1 The Design Hierarchy.2.2 Integrated Circuit Layers- A view of ICs as a set of patterned material layers,a physical implementation of signal control or processing, power supply and logic convention, Metal and insulator layers of a
chip,Patterned metal layers and 3D structures,importance of shapes and sizes of each pattern,a role of a layout editor as a CAD tool , physical design constrained by fabrication process. 2.3 Photolithography and Pattern Transfer Photolithography to translate on-screen drawings to a physical structure, resolution and a limiting factor,the sequence to create pattern,contraints by photolithography and effects on layout designs, a mask or reticle and its use, photoresist,discussion of minimum feature size and deep submicron,importance of cleaning and a clean room.2.4 Planarization 2.5 Electrical Characteristics ,details and formulas,example of R,C calculation.2.6 Silicon Characteristics- intrinsic density, resistivity and electron or hole mobility, different behavior of electrons and holes, capacitance of a line and a pn junction.2.7 Overview of Layout Design creation of patterns on every layer and defining stacked structure of electronic switching devices and wiring, characteristics of conducting and insulating layers,a set of rules,layers stack and 3D structures,Layout Versus Schematic(LVS) check,circuit extraction,a listing of electronic elements, wiring details and parasitics, shapes and sizes of material layers and final electrical characteristics.
- Chapter 3 CMOS Technology--A Basis for Design(27 pages) 3.1 Meet the MOSFETs 3.2 CMOS Fabrication- CMOS fabrication sequence, order of layers and combination, specifics of the process,each patterning step and a separate mask,p-type silicon wafer as the starting point, detailed explanation of each mask used. 3.3 Submicron CMOS Processes- Moore's Law and Integration Levels, Yield- explanation,definition of the yield Y of a process,simplest estimate of yield as a function of die area and defect density. 3.4 Process Technologies 3.5 Masks and Layout 3.6 MOS Layout Generator 3.7 Chapter Summary and Roadmap.
- Chapter 4 Using a Layout Editor--Fundamental Concepts (18 pages) Physical design based on characteristics of process flow,a role of a layout editor, fundamental concepts of drawing and editing layers. Lambda-Based Layout. Rectangles and Polygons,The MOS Layout Generator Revisited, Units in dialog box,lambda box and lambda measurements,Summary.
- Chapter 5 CMOS Design Rules--Guidelines for Layout (23 pages) Design rules as a set of specifications to govern the layout of masking layers,presents the set of scalable CMOS rules. 5.1 Types of Rules 5.2 The SCMOS Design Rule Set 5.3 FET Layout
- Chapter 6 MOSFETs--Operation and Analytical Models (26 pages) Speed of a digital chip relates to transistors' electrical characteristics as functions of the layout and processing technology.The chapter explains the basic operation of FETs and how the layout affects performance.6.1 MOSFET Operation 6.2 MOSFET Switch Models 6.3 The Square Law Model 6.4 MOSFET Parasitics 6.5 Comments on Device Layout-Selection of W and affecting device transconductances,transistor linearized resistances and all parasitic capacitances, the device transconductance and maximum current,electrical characteristics and parasitics as limiting factors on speed of switching.
- Chapter 7 MOSFET Modeling with SPICE (23 pages) Behavior of MOSFETs under time-varying conditions and limitation of the analytical models,complexity of submicron device physics,computer simulations and basic CAD models of FETs to simulate transistor behavior. 7.1 SPICE Levels 7.2 MOSFET Modeling 7.3 Circuit Extraction 7.4 Spice Level 3 and BSIM4 Equations- a summary of the Level3 and BSIM4 equations with relevant parameter lists.
And much more content not detailed below:
- Chapter 8 CMOS Logic Gates--Design and Layout (41 pages) The topology and layout of circuits for basic logic gates.
- Chapter 9 Standard Cell Design--Layouts and Wiring (22 pages) VLSI systems from primitive components using concepts of repetition and structure regularity,Standard cell design by using a collection of logic cells to create more complex networks.
- Chapter 10 Storage Elements--Design and Layout (15 pages) Common CMOS storage circuits such as basic latches and flipflops and physical design.
- Chapter 11 Dynamic Logic Circuits--Basic Principles (14 pages) Dynamic CMOS logic circuits for designing high-speed cascades, eliminates slow pFETs and uses a clocking signal for both gate operation and data synchronization,large power dissipation in some cases.
- Chapter 12 Interconnect--Routing and Modeling (20 pages) Interconnect complexity as a limiting factor in VLSI design, electrical time delay in a line, electrically induced crosstalk and limited interconnect density.
- Chapter 13 System Layout--Physical Design of the Chip (23 pages) Fabrication and mounting into a package,large-scale physical design and important aspects.
- Chapter 14 SOI Technology--Introduction to Basics (12 pages) This is the overview chapter for some main features of SOI technology. SOI used for various applications, such as radiation hardened circuits,recent development of CMOS SOI and high-speed design operation.
- Chapter 15 Digital System Design 1 (28 pages) A higher level discussion of logic design and digital system design, using a program for simulation,test and verification of the design and for abstract description, information transfer to layout,an example of design automation.
- Chapter 16 Digital System Design 2-Design Flow Examples (22 pages) some examples of system development using the design flow of the programs for illustration of the concepts of repetition and regularity in layout.
- Chapter 17 Capacitors and Inductors On-Chip Passive Elements (12 pages) On-chip passive elements and technique of generating an inductor layout geometry.
- Chapter 18 Analog CMOS Circuits Layout Basics (17 pages) Concern of analog CMOS design toward frequency response, biasing and linearity, importance of component matching,problem of parasitics, the chapter gives a brief introduction to some common analog CMOS circuits.