This handbook provides a comprehensive treatment of area-array interconnections for both chips and microelectronic packages in terms of optimizing densification, functionality and reliability. It provides comparisons with alternative and competing technologies, clearly defining cost versus benefit tradeoffs and strategies. Process details are defined in the order of their typical manufacturing sequence, indicating tooling requirements and potential yield detractors. In addition, the handbook has individual chapters devoted ...
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This handbook provides a comprehensive treatment of area-array interconnections for both chips and microelectronic packages in terms of optimizing densification, functionality and reliability. It provides comparisons with alternative and competing technologies, clearly defining cost versus benefit tradeoffs and strategies. Process details are defined in the order of their typical manufacturing sequence, indicating tooling requirements and potential yield detractors. In addition, the handbook has individual chapters devoted to supporting disciplines that play a key role in satisfying the requirements of microelectronic package applications: efficient thermal-dissipation techniques, metallurgical and mechanical characteristics of interconnections and electrical design strategies. Area-array technology at both die and chip carrier levels offers the best opportunity of satisfying the demanding performance requirements that users at all levels of the product spectrum have come to expect.
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