Advanced ASIC Chip Synthesis: Using Synopsys??? Design Compiler??? Physical Compiler??? and PrimeTime???, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools, used to ...
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Advanced ASIC Chip Synthesis: Using Synopsys??? Design Compiler??? Physical Compiler??? and PrimeTime???, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.
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Add this copy of Advanced ASIC Chip Synthesis: Using Synopsys® Design to cart. $232.48, like new condition, Sold by GreatBookPrices rated 4.0 out of 5 stars, ships from Columbia, MD, UNITED STATES, published 2013 by Springer-Verlag New York Inc..
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Fine. XXVI, 328 p. Intended for professional and scholarly audience. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
Add this copy of Advanced ASIC Chip Synthesis: Using Synopsys® Design to cart. $234.83, new condition, Sold by GreatBookPrices rated 4.0 out of 5 stars, ships from Columbia, MD, UNITED STATES, published 2013 by Springer-Verlag New York Inc..
Choose your shipping method in Checkout. Costs may vary based on destination.
Seller's Description:
New. XXVI, 328 p. Intended for professional and scholarly audience. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
Add this copy of Advanced ASIC Chip Synthesis: Using Synopsys® Design to cart. $234.84, new condition, Sold by Ingram Customer Returns Center rated 5.0 out of 5 stars, ships from NV, USA, published 2013 by Springer-Verlag New York Inc..
